As computers have been developed to perform a greater number of instructions at greater speeds, many types of architectures have been developed to optimize this process. For example, a reduced instruction set computer (RISC) device utilizes fewer instructions and greater parallelism in executing those instructions to ensure that computational results will be available more quickly than the results provided by more traditional data processing systems. In addition to providing increasingly parallel execution of instructions, some data processing systems implement out-of-order instruction execution to increase processor performance. Out-of-order instruction execution increases processor performance by dynamically allowing instructions dispatched with no data dependencies to execute before previous instructions in an instruction stream that have unresolved data dependencies. In some data processing systems, instructions are renamed and instruction sequencing tables, also referred to as re-order buffers, facilitate out-of-order execution by reordering instruction execution at instruction completion time.
Re-order buffer devices are also used to allow speculative instruction execution. Therefore, data processing systems which support speculative instruction execution can be adapted for out-of-order execution with the addition of relatively minimal hardware. A portion of this added hardware includes issue logic which is used to determine a time and order that instructions should be issued. Such issue logic can be extremely complex since the dependencies of instructions and a state of a pipeline in which the instructions are being executed must be examined to determine a time at which the instruction should issue. If the issue logic is not properly designed, such issue logic can become a critical path for the data processing system and limit the frequency of instruction execution such that performance gains which could be achieved by out-of-order issue are destroyed.
Therefore, a need exists for an out-of-order issue mechanism that efficiently issues independent instructions in a timely manner and that does not limit a frequency with which the processor executes instructions.